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    2. 參數資料
      型號: TMJ320C6211GNY167
      廠商: Texas Instruments, Inc.
      元件分類: 數字信號處理
      英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
      中文描述: 定點數字信號處理器
      文件頁數: 74/83頁
      文件大?。?/td> 1176K
      代理商: TMJ320C6211GNY167
      TMS320C6211, TMS320C6211B
      FIXED-POINT DIGITAL SIGNAL PROCESSORS
      SPRS073K
      AUGUST 1998
      REVISED MARCH 2004
      74
      POST OFFICE BOX 1443
      HOUSTON, TEXAS 77251
      1443
      MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
      timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
      (see Figure 41)
      NO.
      150
      167
      UNIT
      MASTER
      MIN
      26
      4
      SLAVE
      MIN
      2
      6P
      6 + 12P
      MAX
      MAX
      4
      5
      t
      su(DRV-CKXH)
      t
      h(CKXH-DRV)
      Setup time, DR valid before CLKX high
      Hold time, DR valid after CLKX high
      ns
      ns
      P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
      For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
      switching characteristics over recommended operating conditions for McBSP as SPI master or
      slave: CLKSTP = 10b, CLKXP = 1
      (see Figure 41)
      NO.
      PARAMETER
      150
      167
      UNIT
      MASTER
      §
      MIN
      T
      9
      H
      9
      9
      SLAVE
      MIN
      MAX
      T + 9
      H + 9
      MAX
      1
      2
      3
      t
      h(CKXH-FXL)
      t
      d(FXL-CKXL)
      t
      d(CKXL-DXV)
      Hold time, FSX low after CLKX high
      Delay time, FSX low to CLKX low
      #
      Delay time, CLKX low to DX valid
      Disable time, DX high impedance following last data bit from
      CLKX high
      ns
      ns
      ns
      9
      6P + 4
      10P + 20
      6
      t
      dis(CKXH-DXHZ)
      H
      9
      H + 9
      ns
      7
      t
      dis(FXH-DXHZ)
      Disable time, DX high impedance following last data bit from
      FSX high
      2P + 3
      6P + 20
      ns
      8
      t
      d(FXL-DXV)
      Delay time, FSX low to DX valid
      4P + 2
      8P + 20
      ns
      P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
      For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
      §
      S =
      Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
      =
      Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
      T =
      CLKX period = (1 + CLKGDV) * S
      H =
      CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
      = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
      L =
      CLKX low pulse width
      = (CLKGDV/2) * S if CLKGDV is even
      = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
      FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
      and FSR is inverted before being used internally.
      CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
      CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
      #
      FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
      (CLKX).
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      參數描述
      TMJ320C6211GNZ167 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS
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